1. Field of the Invention
The present invention relates to a delay locked loop (DLL) circuit in which comparison is made between the phase of an input signal and that of a signal obtained by causing the input signal to delay, and then a delay stage is adjusted so that their timings become equal.
2. Description of the Background Art
FIG. 15 is a diagram illustrating the configuration of a conventional DLL circuit. As shown in FIG. 15, a phase comparator (PFD) 23 compares the phase of an input signal CLKIN as a reference clock signal and the phase of a feedback signal FBCLK as a real use clock signal, to output an up signal UP and a down signal DWN to a charge pump (CP) 6. A feedback signal FBCLK is a signal which is obtained after an input signal CLKIN propagates a delay line 9 and an internal circuit 17, and therefore, a delay time occurs due to the propagation through the delay line 9 and the internal circuit 17. The internal circuit 17 is an internal circuit of clock processing system, e.g., clock trees.
The CP 6 supplies a current I6 to a low-pass filter (LPF) 28, based on an up signal UP and a down signal DWN, and drains it from the LPF 28. That is, the CP 6 supplies a current I6 when an up signal UP is "H" and drains a current I6 from the LPF 28 when a down signal DWN is "H".
The LPF 28 integrates a current I6 and, based on its result (a potential V1 of a node N1), outputs a delay adjusting signal S28 to the delay line 9. When an external reset signal RST is at "H" level, the LPF 28 outputs a delay adjusting signal S28 indicating that a delay time due to the delay line 9 is minimized, irrespective of a current I6.
The delay line 9 causes an input signal CLKIN to delay a delay time DT9 indicated by a delay adjusting signal S28, to output a delay input signal CLKOUT as a delay reference clock signal. A feedback signal FBCLK that is a signal obtained by causing a delay input signal CLKOUT outputted from the delay line 9 to delay in passing through the internal circuit 17, is used as a clock for controlling the timing of a data latch 18 or the like, and is also fed back to the phase comparator 23.
In this DLL circuit 10, a DLL comprises the phase comparator 23, the CP 6, the LPF 28 and the delay line 9, and a delay time DT9 of the delay line 9 is adjusted so that the phase of an input signal CLKIN matches that of a feedback signal FBCLK. It is therefore possible to latch data DATA in synchronization with the input signal CLKIN, based on a feedback signal FBCLK, regardless of a delay time due to the internal circuit 17.
FIG. 16 is a block diagram showing the internal configuration of a phase comparator 23. Such a comparator is for example disclosed in Symposium on VLSI Circuits Digest of Technical Papers, 94, pp.129-130. As shown in FIG. 16, phase comparison sections 20U, 20D output an up signal UP and a down signal DWN, respectively, based on the phase difference between a signal obtained from a clock input CLK and a signal obtained from a feedback input FB.
In the phase comparison section 20U the clock input CLK receives an input signal CLKIN, the feedback input FB receives a feedback signal FBCLK, and an inhibit input INHB receives a down signal DWN. In the phase comparison section 20D the clock input CLK receives a feedback signal FBCLK, the feedback input FB receives an input signal CLKIN, and an inhibit input INHB receives an up signal UP.
FIG. 17 is a circuit diagram showing the internal configuration of a phase comparison section 20U (20D). As shown in FIG. 17, an input of an inverter 41 is connected to a clock input CLK. PMOS transistor Ql and NMOS transistors Q2, Q3 are interposed in series from a power supply to a ground level. The gates of PMOS transistor Q1 and the NMOS transistor Q3 are connected in common to an output of the inverter 41.
PMOS transistor Q4 and NMOS transistors Q5, Q6 are interposed in series from a power supply to a ground level. NMOS transistor Q7 is connected in parallel to the NMOS transistor Q5. The gates of the PMOS transistor Q4 and the NMOS transistor Q6 are connected in common to the drain of the PMOS transistor Q1 (the NMOS transistor Q2), the gate of the NMOS transistor Q5 is connected to a feedback input FB, and the gate of the NMOS transistor Q7 is connected to an inhibit input INHB.
In addition, PMOS transistor Q8 and NMOS transistors Q9, Q10 are interposed in series from a power supply to a ground level. The gates of the PMOS transistor Q8 and the NMOS transistor Q10 are connected in common to the drain of the PMOS transistor Q4 (the NMOS transistors Q5, Q7), the gate of the NMOS transistor Q9 is connected to the drain of the PMOS transistor Q1, the drain of the PMOS transistor Q8 (the NMOS transistor Q9) is connected to an input section of an inverter 42 and is also connected to the gate of the NMOS transistor Q2.
A signal obtained from an output of the inverter 42 becomes an up signal UP (a down signal DWN).
FIGS. 18 and 19 are a timing diagram illustrating a phase comparison operation of a phase comparator 23 with the configuration as shown in FIGS. 16 and 17. As shown in FIG. 18, when the phase of a feedback signal FBCLK is delayed than that of an input signal CLKIN, an up signal UP of a phase comparison section 20U becomes "H" for a period of time from the rise of the input signal CLKIN to the rise of the feedback signal FBCLK, while a down signal DWN of a phase comparison section 20D becomes "L" at all times.
As a result, the up signal UP and the down signal DWN of the phase comparator 23 cause the phase of the feedback signal FBCLK to advance, so that a delay time DT9 due to the delay line 9 is decreased by a CP 6 and an LPF 28.
Referring to FIG. 19, when the phase of a feedback signal FBCLK is advanced than an input signal CLKIN, a down signal DWN of a phase comparison section 20D becomes "H" during a period of time from the rise of feedback signal FBCLK to the rise of the input signal CLKIN, while an up signal UP of a phase comparison section 20U becomes "L" at all times.
As a result, the up signal UP and the down signal DWN of the phase comparator 23 causes the phase of the feedback signal FBCLK to delay, so that a delay time DT9 due to the delay line 9 is increased by the CP 6 and the LPF 28.
In the conventional DLL circuit, however, a wide variety of phase relations between an input signal CLKIN and a feedback signal FBCLK are determined by a delay time due to the internal circuit 17. Therefore, it is impossible for a phase comparator 23 to judge at the time of initial operation whether a phase should be advanced or delayed.
To obtain a variable delay time range sufficient for synchronization whatever phase relations are present between an input signal CLKIN and a feedback input FB (e.g., at least two times or more of a signal period T of an input signal CLKIN), the delay line 9 of the conventional DLL circuit is required to have a large number of delay stages. This causes an increase in the circuit scale and dissipation power of the DLL circuit.
Lock deviation phenomenon occurred when a delay time due to an internal circuit 17 fluctuates during operation is described by referring to FIG. 20. In conventional DLL circuits, in order to match the phase of an input signal CLKIN with that of a feedback signal FBCLK, the total delay time of a delay time DT17 due to an internal circuit 17 and a delay time DT9 due to a delay line 9 is always arranged to be integral multiples of a period T of an input signal CLKIN. For a narrow variable delay time range of the delay line 9, if the delay time DT17 due to the internal circuit 17 fluctuates gradually because of circumstances, e.g., temperature, it is outside the variable delay time range of the delay line 9 with respect to shifts of more than a certain value, making it impossible to match phases.
As shown in FIG. 20, suppose that the total delay time (DT17+DT9) of a delay time DT17 of the internal circuit 17 and a delay time DT9 of the delay line 9 is in synchronization with kT (k is a natural number) at time t0, but the delay time DT17 of the internal circuit 17 increases with the passage of time.
In this case, since the phase of a feedback signal FBCLK is delayed than that of an input signal CLKIN, a DLL circuit 10 operates to advance the phase, i.e., to decrease the delay time DT9 of the delay line 9. Until time t1, the total delay time, (DT17+DT9)=kT, is given by that an increase in the delay time DT17 is compensated by a decrease in the delay time DT9, thereby it is possible to synchronize the input signal CLKIN with the feedback signal FBCLK
However, if the delay time DT17 is further increased after time t1, it is outside the variable delay time range of the delay line 9 (the region shown by diagonal in FIG. 20). That is, even when the delay time DT9 of the delay line 9 is set to be a minimum delay time .DELTA.DT, it follows that (DT17+DT9)&gt;kT. It is therefore impossible to synchronize the input signal CLKIN with the feedback signal FBCLK by advancing the phase of the feedback signal FBCLK This phenomenon is referred to as lock deviation phenomenon.
To solve lock deviation phenomenon, it is also necessary that the number of delay stages of a delay line 9 is large enough and a variable delay time range is increased considerably. This leads to a large scaled circuit configuration and an increased dissipation power, as stated earlier. Also, the resistance to noise of the delay line 9 may be affected with increasing the number of stages of the delay line 9.